1. Field of the Invention
The present invention relates to an insulated gate thin film transistor formed on an insulating material (e.g., glass) or a material such as a silicon wafer having thereon an insulating film (e.g., silicon oxide), and to a method for fabricating the same. The present invention is particularly effective for thin film transistors fabricated on a glass substrate having a glass transition temperature (deformation temperature or deformation point) of 750° C. or less. The thin film transistor according to the present invention is useful for driver circuits of, for example, active matrix liquid crystal displays and image sensors, as well as for three dimensional integrated circuits.
2. Description of the Related Art
Thin film transistors (referred to simply hereinafter as “TFTs”) are widely employed for driving, for example, liquid crystal displays of active matrix type and image sensors. TFTs of crystalline silicon having a higher electric field mobility are also developed as an alternative for amorphous silicon TFTs to obtain high speed operation. However, TFTs with further improved device characteristics and durability can be obtained by forming an impurity region having a high resistance (high resistance drain; HRD).
FIG. 4A shows a cross section view of a conventional TFT having an HRD. The active layer comprises low resistance regions 1 and 5, a channel forming region 3, and high resistance regions 2 and 4 formed therebetween. A gate insulating film 6 is provided to cover the active layer, and a gate electrode 7 is formed on the channel forming region 3 through the gate insulating film 6. An interlayer dielectric 8 is formed to cover the gate electrode 7, and source/drain electrodes 9 and 10 are connected to the low resistance regions 1 and 5. At least one of the elements selected from oxygen, nitrogen, and carbon is introduced into the high resistance regions 2 and 4.
The introduction of at least one of the elements above, however, requires the use of photolithography. Thus, it is difficult to form high resistance regions on the edge portion of the gate electrode in a self-alignment; hence, the TFTs are fabricated at a low yield, and moreover, the TFTs thus obtained are not uniform in quality.